Acquires

SASIC Technologies Private Limited is a premier semiconductor engineering services and solutions provider that blends technology, creativity to help customers transform ideas into world-class products. We offer engineering expertise in the areas of RTL design, Verification, Physical Design, FPGA and Embedded systems under one roof.

Execution Innovation Integrity Flexibility of our Systems Customer Services Quality Fast Turnaround Time Wide Exposure SASIC brings with them set of customer delight values

Sasic brings with them

10 clients total number now clients 20+

Sasic’ Expertise

RTL Design

  • Architecture development
  • RTL development and integration
  • Synthesis for ASIC or FPGA and Static Timing Analysis
  • FPGA implementation or ASIC prototyping
  • Formal verification and equivalence check in.

Verification IP

  • VIP development for interfaces such as Ethernet, USB, AHB/AXI, I2C, PMBus-AVS etc
  • VIP development using HVL such as SystemVerilog.
  • VIP development using latest methodologies such as UVM, OVM, VMM, etc..

SOC Verification

  • Verification planning including architecture for re-use
  • Low power static verification
  • Formal verification
  • Deployment of advanced verification methodologies such as UVM
  • Test-bench generation
  • Integration of protocol-specific VIP

AMS Verification

  • Verification planning including architecture for re-use
  • Low power static verification
  • Formal verification
  • Deployment of advanced verification methodologies such as UVM
  • Test-bench generation
  • Integration of protocol-specific VIP

FPGA

  • Design using HDL, including System Verilog Verilog, VHDL, C/C++
  • Logic Synthesis Integration of modules
  • Complex multi million gate design
  • Static timing analysis
  • Design translation
  • Partitioning
  • I/O planning and analysis
  • Clock optimization
  • Synthesis optimization

IP Verification

  • Test bench design / development
  • Verification IP development
  • Functional Verification
  • Model-based Verification
  • Hardware-Software Co-Verification
  • Coverage-driven Verification
  • Assertion-based Verification
  • Constrained-Random Verification
  • Test bench migration

EDA Validation

  • Language testing (LRM compliance)
  • Methodology adoption
  • Release qualification
  • Migration experiments, leading to prioritized set of features needed in next major release of the tool
  • GUI testing
  • Performance testing
  • SystemVerilog compilers, simulators
  • PSL
  • Model checkers
  • VHDL-Verilog mixed simulations
  • Linting tools
  • FPGA flow tools
  • ESL tools