Senior Verification Engineer
CoQube is founded by a team of semiconductor and operations management professionals with extensive industry experience. CoQube works with marquee semiconductor product companies in servicing their niche requirements, with special focus on turnkey semiconductor development.
We are looking for energetic, passionate, experienced candidates, with an eagerness to lead and implement the Vision and Mission of the company.
CoQube is seeking an experienced ASIC verification engineer for the position of Senior Verification Engineer. We offer flexible and conducive work environment, with compensation matched to industry.
Job Responsibilities –
- Architect and develop verification environment and testbench components such as BFMs and checkers.
- Verify design in unit level environment using directed and constrained random testing, assertion-based verification, formal analysis, and functional verification.
- Write functional cover groups and cover points for coverage closure. Perform RTL code coverage, assertion coverage, functional coverage and gate level simulations
- Maintain verification plans for highly complex ASIC/SoC blocks and products.
- Perform successful chip/block level verification of ASIC block.
- Perform coding of reusable testbench components based on advanced verification methodologies, such as SV/UVM.
- Perform analysis of coverage metrics to ensure conformity with design specification and verification plan.
- Take part in review of design specification, codes and verification plan.
- Oversee regression management to ensure coverage goals are met appropriately.
- Ensure high quality verification by working closely with algorithm development team and ASIC designers.
- Interact with Project Manager to ensure timely delivery of products.
Additional Responsibilities –
- Drive and adopt new verification methodologies and flows for efficiency improvements.
- Work with SoC, Validation and SW teams to resolve queries and issues in module integration and usage. Guide/Mentor junior engineers on project execution
- Assist validation team on board-level test issues.
- Educate design team on verification methodology
| Years of experience | 05-10 |
| Hands-on technical expertise in ASIC/ SoC Verification | Mandatory |
| Strong verbal and written communication skills | Mandatory |
| Program/ Project Management experience | Desired |
| Team Leadership experience | Desired |
Required Skills –
- 5-10years, equivalent experience in ASIC design and verification.
- Familiar with System Verilog Assertions, Code and Functional Coverage and Formal verification techniques.
- Experience in verifying designs at system level and block level using constrained random verification.
- Expert in System Verilog and OVM/UVM based verification.
- Strong experience in ASIC design verification flows and DV methodologies.
- Expert in coding SV Testbench, drivers, monitors, scoreboards, checkers
- Highly motivated and be able to work both independently and as a member of team.
- Strong and independent design debugging capability.
- Strong programming and scripting language capability.
- Expert in using verification tools like VCS, IUS, modelsim, Debussy etc.