CoQube Semiconductor has been acquired by Alten Calsoft Labs (India) ltd in July 2021. Please feel free to contact info@coqube.com if you need more details or any other support requirements.
CoQube Semiconductor is founded by a team of semiconductor and operations management professionals with extensive industry experience of 10 decades. We are well versed with all aspects of semiconductor product development. CoQube works with marquee semiconductor product companies in servicing their niche requirements, with special focus on architecture, micro-architecture, digital design & verification.
Activities We Perform
We deliver best-in-class semiconductor solutions through a professionally mature team which has expertise in end-to-end ASIC/ SoC development.
Team CoQube has worked on products ranging from a few 1000 gates to those with a few billion transistors on them. We hope to leverage that experience in solving our clients key design requirements, with a high emphasis on deliverable quality.
Architecture
- Design Partitioning
- Performance Analysis
- Power Analysis
- Area Analysis
- Die size Estimation
- Use-Case Validation
Micro-Architecture
- Finite State Machine Analysis
- Control Path & Data Path Analysis
- Timing Diagrams
- Port List Development
- IP Selection
RTL Development
- IP Development in Verilog/ VHDL/ System Verilog
- Matlab/ C Translation to bit accurate RTL
RTL Integration
- Lint
- Clock Domain Crossing Check (CDC)
- Power Aware Design Integration (CPF/UPF)
- Logic Equivalence Check (LEC)
Digital Verification
- Environment Development( SV/UVM/Verilog)
- Metric Driven Verification
- Power Aware Simulations
- Gate Level Simulations
AMS Verification
- WReal Simulation
- Digital Mixed Signal Verification
- Analog Mixed Signal Verification
Synthesis
- Constraints Development
- Logic Synthesis
- Pre-Placement Timing Analysis
Design For Testability
- Scan Stitching
- Test Coverage Analysis
- Scan Constraint Development
Place & Route
- Placement / Routing
- Clock Tree Synthesis
- Physical Verification
- RC Extraction
Static Timing Analysis
- Timing Sign-off
- Constraints refinement and sign-off
Product Validation
- Pre-Silicon Validation
- Post-Silicon Validation
- FPGA Emulation
Performance Analysis
Power Analysis
Area Analysis
Die size Estimation
Use-Case Validation
Control Path & Data Path Analysis
Timing Diagrams
Port List Development
IP Selection
Matlab/ C Translation to bit accurate RTL
Clock Domain Crossing Check (CDC)
Power Aware Design Integration (CPF/UPF)
Logic Equivalence Check (LEC)
Metric Driven Verification
Power Aware Simulations
Gate Level Simulations
Digital Mixed Signal Verification
Analog Mixed Signal Verification
Logic Synthesis
Pre-Placement Timing Analysis
Test Coverage Analysis
Scan Constraint Development
Clock Tree Synthesis
Physical Verification
RC Extraction
Constraints refinement and sign-off
Post-Silicon Validation
FPGA Emulation